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1 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation sp690t/s/r, sp802t/s/r, sp804t/s/r, and sp805t/s/r 3 . 0 v / 3 . 3 v l o w p o w e r m i c r o p r o c e s s o r s u p e r v i s o r y w i t h b a t t e r y s w i t c h - o v e r the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices are a family of microprocessor ( m p) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in m p and digital systems. the series will significantly improve system reliability and operational efficiency when compared to discrete solutions. the features of the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices include a watchdog timer, a m p reset and backup- battery switchover, and power-failure warning; a complete m p monitoring and watchdog solution. the series is ideal for 3.0v or 3.3v applications in portable electronics, computers, controllers, and intelligent instruments and is a solid match for designs where it is critical to monitor the power supply to the m p and its related digital components. refer to sipex's sp690a/692a/802l/802m/805l/805m series for similar devices designed for +5v systems. n reset and reset outputs n reset asserted down to v cc = 1v n reset time delay - 200ms n watchdog timer - 1.6 sec timeout n 40 m a maximum v cc supply current n 1 m a maximum battery supply current n p o w e r s w i t c h i n g 5 0 m a o u t p u t i n v cc m o d e ( 1 . 5 w ) 1 0 m a o u t p u t i n b a t t e r y m o d e ( 1 5 w ) n b a t t e r y c a n e x c e e d v cc i n n o r m a l o p e r a t i o n n precision voltage monitor for power-fail or low-battery warning n available in 8 pin so and dip packages n pin compatible upgrades to max690t/s/r, max802t/s/r, max804t/s/r, max805t/s/r description r e b m u n t r a p t e s e r e v i t c a e v i t c a e v i t c a e v i t c a e v i t c a t e s e r d l o h s e r h t d l o h s e r h t d l o h s e r h t d l o h s e r h t d l o h s e r h t t e s e r y c a r u c c a y c a r u c c a y c a r u c c a y c a r u c c a y c a r u c c a i f p y c a r u c c a y c a r u c c a y c a r u c c a y c a r u c c a y c a r u c c a g o d h c t a w t u p n i t u p n i t u p n i t u p n i t u p n i y r e t t a b - p u k c a b h c t i w s h c t i w s h c t i w s h c t i w s h c t i w s t 5 0 8 / t 0 9 6 p s h g i h / w o l v 5 7 0 . 3 v m 5 7 % 4 s e y s e y t 4 0 8 / t 2 0 8 p s h g i h / w o l v 5 7 0 . 3 v m 0 6 % 2 s e y s e y s 5 0 8 / s 0 9 6 p s h g i h / w o l v 5 2 9 . 2 v m 5 7 % 4 s e y s e y s 4 0 8 / s 2 0 8 p s h g i h / w o l v 5 2 9 . 2 v m 0 6 % 2 s e y s e y r 5 0 8 / r 0 9 6 p s h g i h / w o l v 5 2 6 . 2 v m 5 7 % 4 s e y s e y r 4 0 8 / r 2 0 8 p s h g i h / w o l v 5 2 6 . 2 v m 0 6 % 2 s e y s e y ?
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc ..................................................................................-0.3v to 6.0v v batt ................................................................................-0.3v to 6.0v all other inputs (note 1).................................-0.3v to the higher of v cc or v batt continuous input current: v cc ..................................................................................100ma v batt ..................................................................................20ma gnd..................................................................................20ma wdi, pfi...........................................................................20ma continuous output current: reset, reset, pfo.........................................................20ma v out ......................................................................................100ma power dissipation per package: 8pin nsoic (derate 6.14mw/ c above +70 c)..............500mw 8pin pdip (derate 11.8mw/ c above +70 c)..............1,000mw storage temperature........................................-65 c to +160 c lead temperature(soldering,10sec).............................................+300 c esd rating........................................................4kv human body model specifications v cc = 3.17v to 5.50v for the sp690t/sp80_t, v cc = 3.02v to 5.50v for the sp690s/sp80_s, v cc = 2.72v to 5.50v for the sp690r/sp80_r, v batt = 3.60v, and t a = t min to t max unless otherwise noted. typical values taken at t amb = +25 o c. s r e t e m a r a p . n i m . p y t . x a m s t i n u s n o i t i d n o c , e g n a r e g a t l o v g n i t a r e p o 0 . 1 5 . 5 s t l o v v c c v r o y r e t t a b , e t o n 1 v c c i , t n e r r u c y l p p u s y l p p u s 5 2 0 4 m a i g n i d u l c x e t u o v c c y r e t t a b n i t n e r r u c y l p p u s e d o m p u k c a b 0 2 0 4 m a v c c v , v 0 . 2 = y r e t t a b , v 3 . 2 = i g n i d u l c x e t u o v y r e t t a b n i t n e r r u c y l p p u s , e d o m y n a e t o n 2 4 . 0 1 m a i g n i d u l c x e t u o v y r e t t a b e t o n , t n e r r u c e g a k a e l 3 1 0 0 . 0 5 . 0 m a v y r e t t a b e t o n , t n e r r u c e g a k a e l 4 1 . 0 - 2 0 . 0 m a v > v 3 . 3 c c v > y r e t t a b v 2 . 0 + v , e g a t l o v t u p t u o t u o v c c 3 0 . 0 - v c c 3 . 0 - v c c 5 1 0 0 . 0 - v c c 5 7 0 0 . 0 - v c c 5 7 0 . 0 - v c c 3 0 0 0 . 0 - v a m 5 = i i t u o a m 0 5 = i t u o 0 5 2 = m v , a c c v 5 . 2 > v t u o e d o m p u k c a b - y r e t t a b n i v y r e t t a b 2 0 . 0 - v y r e t t a b 5 4 0 0 . 0 - v y r e t t a b 8 1 0 . 0 - v y r e t t a b 5 1 . 0 - v i t u o v , a 0 5 2 = y r e t t a b v 3 . 2 = i t u o v , a m 1 = y r e t t a b v 3 . 2 = i t u o b v , a m 0 1 = y r e t t a v 3 . 3 = , d l o h s e r h t h c t i w s y r e t t a b v c c g n i l l a f 5 6 0 . 0 0 3 . 2 5 2 0 . 0 0 4 . 2 0 5 . 2 v v y r e t t a b v - c c v , w s v > c c 5 e t o n , v 5 7 . 1 > v y r e t t a b v > c c 6 e t o n , , d l o h s e r h t h c t i w s y r e t t a b v c c 7 e t o n , g n i s i r v t e s e r e h t o t l a c i t n e d i e r a s e u l a v v t a s e u l a v d l o h s e r h t c c g n i s i r
3 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation s r e t e m a r a p .n i m . p y t . x a m s t i n u sn o i t i d n o c v , d l o h s e r h t t e s e r t s r 8 e t o n 0 0 . 3 0 0 . 3 5 8 . 2 5 8 . 2 5 5 . 2 5 5 . 2 5 7 0 . 3 5 8 0 . 3 5 2 9 . 2 5 3 9 . 2 5 2 6 . 2 5 3 6 . 2 5 1 . 3 7 1 . 3 0 0 . 3 2 0 . 3 0 7 . 2 2 7 . 2 v v , t 5 0 8 /t 0 9 6 p s c c g n i l l a f v , t 5 0 8 /t 0 9 6 p s c c g n i s i r v , s 5 0 8 /s 0 9 6 p s c c g n i l l a f v , s 5 0 8 /s 0 9 6 p s c c g n i s i r v , r 5 0 8 /r 0 9 6 p s c c g n i l l a f v , r 5 0 8 /r 0 9 6 p s c c g n i s i r 0 0 . 3 0 0 . 3 8 8 . 2 8 8 . 2 9 5 . 2 9 5 . 2 5 7 0 . 3 5 8 0 . 3 5 2 9 . 2 5 3 9 . 2 5 2 6 . 2 5 3 6 . 2 2 1 . 3 4 1 . 3 0 0 . 3 2 0 . 3 0 7 . 2 2 7 . 2 v v , t 4 0 8 /t 2 0 8 p s c c g n i l l a f v , t 4 0 8 /t 2 0 8 p s c c g n i s i r v , s 4 0 8 /s 2 0 8 p s c c g n i l l a f v , s 4 0 8 /s 2 0 8 p s c c g n i s i r v , r 4 0 8 /r 2 0 8 p s c c g n i l l a f v , r 4 0 8 /r 2 0 8 p s c c g n i s i r t e s e r t, d o i r e p t u o e m i t p w 0 4 1 0 0 2 0 8 2 s m v , e g a t l o v t u p t u o o f p , t e s e r h o v c c 3 . 0 - v c c 5 1 . 0 - v i e c r u o s a 0 3 = v , e g a t l o v t u p t u o o f p , t e s e r l o 6 0 . 0 03 . 0 v i k n i s e r e h w _ 2 0 8 / _ 0 9 6 p s , a m 2 . 1 = v c c v = t s r m u m i n i m v , e g a t l o v t u p t u o o f p , t e s e r l o 3 1 . 0 03 . 0 v v y r e t t a b v, v 0 = c c i , v 0 . 1 = k n i s a 0 4 = v , e g a t l o v t u p t u o t e s e r l o 6 0 . 0 0 3 . 0 v i k n i s e r e h w _ 5 0 8 / _ 4 0 8 p s , a m 2 . 1 = v c c v = t s r m u m i x a m , t n e r r u c e g a k a e l t u p t u o t e s e r 1 1 e t o n 1 - 1 - m a v y r e t t a b v, v 0 = c c v = t s r , m u m i n i m v t e s e r v r o v 0 = c c i , t n e r r u c d n g o t t r o h s t u p t u o s o , t e s e r d n a o f p 0 8 1 0 0 5 m a v c c v, v 3 . 3 = h o v 0 = t , t u o e m i t g o d h c t a w d w 2 1 . 1 0 6 . 1 42 . 2 s v c c v 6 . 3 < h t d i w e s l u p i d w 1 m s d l o h s e r h t t u p n i i d w v h i v l i v x 3 . 0 c c v x 7 . 0 c c v t n e r r u c t u p n i i d w 1 - 1 0 . 0 1 m a v < v 0 c c v 5 . 5 < d l o h s e r h t t u p n i i f p 0 0 2 . 1 5 2 2 . 1 5 2 . 1 5 2 . 1 0 0 3 . 1 5 7 2 . 1 v v , _ 5 0 8 / _ 0 9 6 p s c c < v , v 6 . 3 i f p g n i l l a f v , _ 4 0 8 / _ 2 0 8 p s c c < v , v 6 . 3 i f p g n i l l a f t n e r r u c t u p n i i f p 5 2 - 1 0 . 0 5 2 a n v , s i s e r e t s y h i f p h f p 01 0 2 v m v, g n i s i r i f p c c < v 6 . 3 specifications (continued) v cc = 3.17v to 5.50v for the sp690t/sp80_t, v c c = 3.02v to 5.50v for the sp690s/sp80_s, v c c = 2.72v to 5.50v for the sp690r/sp80_r, v b a t t = 3.60v, and t a = t m i n to t m a x unless otherwise noted. typical values taken at t a m b = +25 o c.
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 4 specifications (continued) v cc = 3.17v to 5.50v for the sp690t/sp80_t, v cc = 3.02v to 5.50v for the sp690s/sp80_s, v cc = 2.72v to 5.50v for the sp690r/sp80_r, v batt = 3.60v, and t a = t min to t max unless otherwise noted. typical values taken at t amb = +25 o c. note 1: the following are tested at v batt = 3.6v and v cc = 5.5v: v cc supply current, watchdog functionality, logic input leakage, pfi functionality, and the reset and reset states. the state of reset or reset and pfo is tested at v cc = v cc (min). note 2: tested v batt = 3.6v, v cc = 3.5v and 0v. note 3: leakage current into the battery is tested under the following worst-case conditions: v cc = 5.5v, v batt = 1.8v and at v cc = 1.5v, v batt = 1.0v. note 4: "-" equals the battery-charging current, "+" equals the battery-discharging current. note 5: when v sw > v cc > v batt , v out remains connected to v cc until v cc drops below v batt . the v cc -to-v batt comparator has a small 25mv typical hysteresis to prevent oscillation. note 6: when v batt > v cc > v sw , v out remains connected to v cc until v cc drops below the battery switch threshold, v sw . note 7: v out switches from v batt to v cc when v cc rises above the reset threshold, independent of v batt . switchover back to v cc occurs at the exact voltage that causes reset to go high (on the sp804_ and sp805_ reset goes low). switchover occurs 200ms prior to reset. note 8: the reset threshold tolerance is wider for v cc rising than for v cc falling to accommodate the 10mv typical hysteresis, which prevents internal oscillation. note 9: sp690_ and sp802_ devices only. note 10: sp804_ and sp805_ devices only. note 11: the leakage current into or out of the reset pin is tested with reset asserted (reset output high impedance).
5 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation internal block diagram 1.25v ba ttery switchover circuit pfi wa tchdog timer reset genera tor v cc ba ttery switchover comp ara tor reset comp ara tor 1.25v 1.25v wdi v ba tt pfo reset / reset* sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r *sp804t/s/r and sp805t/s/r only power-f ail comp ara tor 7 5 4 6 8 2 v out gnd 3 1
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 6 pin assignments pin 1 v out output supply voltage for cmos ram. when v cc is above the reset threshold, v out connects to v cc through a p-channel mosfet switch. when v cc falls below the v sw and v battery , v battery connects to v out . connect to v cc if no battery is used. pin 2 v cc +5v supply input pin 3 gnd ground reference for all signals pin 4 pfi power-fail comparator input. when pfi is less than 1.25v or when v cc falls below the v sw , pfo goes low, otherwise pfo remains high. connect to gnd if unused. pin 5 pfo power-fail comparator output. leave open if unused. pin 6 wdi watchdog input. if wdi remains high or low for 1.6 seconds, the internal watchdog timer triggers a reset. the internal watchdog timer clears when reset is asserted or wdi sees a rising or falling edge. the watchdog function cannot be disabled. pin 7 for sp690_/802_ only active-low reset output. whenever reset is triggered by a watchdog timeout, it goes low for 200ms. it stays low whenever v cc is below the reset threshold and re- mains low for 200ms after v cc rises above the reset threshold or when the watchdog triggers a reset. pin 7 for sp804_/805_ only active-high open-drain reset output. the inverse operation of reset. pin 8 v battery backup-battery input. when v cc falls below v sw and v battery , v out switchesfrom v cc to v battery . when v cc rises above the reset threshold, v out reconnects to v cc . v battery may exceed v cc . connect to v cc if no battery is used. v out v cc gnd pfi v ba ttery reset / reset* wdi pfo 1 2 3 4 5 6 7 8 * sp804t/s/r and sp805t/s/r only sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r pinout
7 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation typical characteristics (t amb = 25 o c, unless otherwise noted) figure 1. v cc supply current vs. temperature (normal mode) figure 3. pfi threshold vs. temperature figure 2. battery supply current vs. temperature figure 4. v battery to v out on-resistance vs. temperature figure 5. v cc to v out on-resistance vs. temperature figure 6. reset threshold vs. temperature 40 35 30 25 20 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) s u p p l y c u r r e n t ( m a ) 10000 1000 100 10 1 0.1 -60 -35 -10 15 40 65 90 1 15 140 t emperature ( o c) b a t t e r y s u p p l y c u r r e n t ( n a ) 1.262 1.26 1.258 1.256 1.254 1.252 1.25 1.248 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) p f i t h r e s h o l d ( v o l t s ) 30 25 20 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) v b a t t e r y t o v o u t o n - r e s i s t a n c e ( w ) 3.5 3 2.5 2 1.5 1 0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) o n r e s i s t a n c e ( w ) 3.15 3.13 3.1 1 3.09 3.07 3.05 -60 -35 -10 15 40 65 90 1 15 140 t emperature ( o c) r e s e t t h r e s h o l d ( v o l t s )
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 8 figure 7. reset output resistance vs. temperature figure 9. battery current vs. v cc voltage figure 8. reset timeout vs. temperature figure 10. reset-comparator propagation delay vs. temperature figure 11. v cc to v out vs. output current figure 12. v battery to v out vs. output current 1e-06 decade /div 1e-14 5.000 .0000 v3 .5000/div (v) 1000 100 10 1 1 10 100 i out (ma) v o l t a g e d r o p ( m v ) [ v c c - v o u t ] v cc = 4.5v v ba ttery = 0v 1000 100 10 1 1 10 i out (ma) v o l t a g e d r o p ( m v ) [ v b a t t e r y - v o u t ] v cc = 0v v ba ttery = 4.5v 14000 12000 10000 8000 6000 4000 2000 0 -60 -35 -10 15 40 65 90 1 15 140 t emperature ( o c) r e s e t o u t p u t r e s i s t a n c e ( w ) 185 180 175 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) r e s e t t i m e o u t ( m s ) 30 26 22 18 14 10 -60 -40 -20 0 20 40 60 80 100 120 140 t emperature ( o c) p r o p a g a t i o n d e l a y ( m s )
9 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation figure 15a. sp690a reset response time figure 15b. circuit for the sp690a/802l reset response time gnd reset v cc 30pf v cc 10k w t a = +25 c figure 13a. sp690a reset output voltage vs. supply voltage figure 13b. circuit for the sp690a/802l reset output voltage vs. supply voltage figure 14a. sp805l reset output voltage vs. supply voltage figure 14b. circuit for the sp805 reset output voltage vs. supply voltage gnd reset v cc 330pf v cc 10k w v ba ttery v cc gnd reset v cc 330pf v cc 2k w reset v ba ttery = 0v t a = +25 c 0v 0v 1 t v cc 2v div 1 sec / div reset 0 3.1v [ t ] t 1 1v / div 3.1v 2v reset 10 m s / div v cc 0v 0v 1 1v div reset v cc 1 sec /div
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 10 figure 16a. sp805l reset response time figure 16b. circuit for the sp805 reset response time gnd reset v cc 330pf v cc 10k w v cc figure 17b. circuit for the power-fail comparator response time (fall) figure 17a. power-fail comparator response time (fall) 30pf 1k w pfo +1.25v +5v pfi v cc = +5v t a = +25 c figure 18a. power-fail comparator response time (rise) figure 18b. circuit for the power-fail comparator response time (rise) 30pf 1k w pfo +1.25v +5v pfi v cc = +5v t a = +25 c 0v pfi 1.3v 1.2v 5v 500ns / div pfo v cc = 5v = 0 v battery 2 1 t 1 1.3v 1.2v v cc = 5 = 0 v battery pfi pfo 500ns / div 0v [ t ] 1 t v cc 1v / div 3.1v 2v 10 m s / div reset
11 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation figure 19. timing diagram v cc 0v 3.0v or 3.3v t wp reset reset* pfo v out 3.0v or 3.3v 3.0v or 3.3v v sw v ba ttery =3.6v v rst v sw 0v v ba ttery =pfi=3.6v i out =0ma *sp804t/s/r and sp805t/s/r only; reset externally pulled up to v cc . 0v 0v 3.0v or 3.3v 3.0v or 3.3v 0v
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 12 theory of operation the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices are microprocessor ( m p) supervisory circuits that monitor the power supplied to digital circuits such as microproces- sors, microcontrollers, or memory. the series is an ideal solution for portable, battery-powered equipment that requires power supply monitoring. i m p l e m e n t i n g t h i s s e r i e s w i l l r e d u c e t h e number of components and overall complexity. the watchdog functions of this product family will continuously oversee the operational status of a system. these m p supervisory circuits are not short- circuit protected. shorting v out to ground - excluding power-up transients such as charging a decoupling capacitor - may potentially damage these devices. decouple both v cc and v battery pins to ground by placing 0.1 m f capacitors as close to the device as possible. the operational features and benefits of the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices are described in more detail below. reset output the microprocessor's ( m p's) reset input starts the m p in a known state. when the m p is in an unknown state, it should be held in reset. the sp690t/s/r, sp802t/s/r, sp804t/s/r and s p 8 0 5 t / s / r d e v i c e s a s s e r t r e s e t d u r i n g power-up and prevent code execution errors during power-down or brownout conditions. reset is guaranteed to be a logic low for 0v < v cc < v rst , provided that v battery is greater than 1v. without a backup battery, reset is guaranteed valid for v cc > 1v. once v cc exceeds the reset threshold, an internal timer keeps reset low for the reset timeout period. after this period, reset goes high, as seen in figure 19 . if a brownout condition occurs and v cc dips below the reset threshold, reset goes low. each time reset is triggered, it stays low for the reset timeout period. any time v cc goes below the reset threshold, the internal timer restarts. features the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices provide four key functions: 1. a battery backup switch for cmos ram, cmos microprocessors, or other logic. 2. a reset output during power-up, power-down and brownout conditions. 3. a reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. a 1.25v threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than 3.3v or 3.0v. the sp690t/s/r, sp802t/s/r, sp804t/s/r and sp805t/s/r devices differ in their reset- voltage threshold levels and are ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. the series is a solid match for designs where it is critical to monitor the power supply to the m p and its related digital components. figure 20. typical operating circuit gnd gnd reset nmi i/o line v cc pin 7* pfo wdi v out bus v cc gnd v ba ttery r 2 r 1 unregulated regulated +3.3v or +3.0v v cc 0.1 m f pfi dc lithium battery 3.6v m p cmos ram 0.1 m f reset for the sp690t/s/r and the sp802t/s/r reset for the sp804t/s/r and the sp805t/s/r * sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r
13 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation the watchdog timer can also initiate a reset. refer to the watchdog input section. the sp804t/s/r and sp805t/s/r active-high reset output is open drain and the inverse of the sp690t/s/r and sp802t/s/r reset outputs. reset is also triggered by a watchdog timeout. if wdi remains either high or low for a period that exceeds the watchdog timeout period (1.6 sec), reset pulses low for 200ms. as long as reset is asserted, the watchdog timer remains cleared. when reset comes high, the watch- dog resumes timing and must be serviced within 1.6sec. if wdi is tied high or low, a reset pulse is triggered every 1.8sec (t wd plus t rs ). reset threshold the sp690t and sp805t devices are designed for 3.3v systems with a 5% power-supply tolerance and a 10% system tolerance. except for watchdog faults, reset will not assert as long as the power supply remains above 3.15v (3.3v - 5%). reset is guaranteed to assert before the power supply falls below 3.0v. the sp690s and sp805s devices are designed for 3.3v 10% power supplies. except for watchdog faults, they are guaranteed not to assert reset as long as the supply remains above 3.0v (3.3v - 10%). reset is guaranteed to assert before the power supply fails below 2.85v (v cc - 14%). the sp690r and sp805r devices are optimized for monitoring 3.0v 10% power supplies. reset will not occur until v cc falls below 2.7v (3.0v - 10%), but is guaranteed to occur before the supply falls below 2.55v (3.0v - 15%). the sp802t/s/r and sp804t/s/r devices are respectively similar to the sp690t/s/r and s p 8 0 5 t / s / r d e v i c e s w i t h t i g h t e n e d r e s e t and power-fail threshold tolerances. watchdog input the watchdog circuit monitors the m p's activity. if the m p does not toggle the watchdog input (wdi) within 1.6sec, a reset pulse is triggered. the internal 1.6sec timer is cleared by either a reset pulse or by a transition (low-to-high or high-to-low) at wdi. if wdi is tied high or low, a reset pulse is triggered every 1.8sec (t wd plus t rs ). as long as reset is asserted, the timer remains cleared and does not count. as soon as reset is de-asserted, the timer starts counting. unlike the 5v sp690a series, the watchdog function cannot be disabled. power-fail comparator the power-fail comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). the pfi input is compared to an internal 1.25v. if pfi is less than v pft , pfo goes low. the power-fail comparator turns off and pfo goes low when v cc falls below v sw on power-down. the power-fail comparator turns on as v cc crosses v sw on power-up. if the comparator is not used, connect pfi to ground and leave pfo unconnected. backup-battery switchover in the event of a brownout or power failure, it may be necessary to preserve the contents of ram. with a backup battery installed at v battery , the devices automatically switch ram to backup power when v cc fails. this family of m p supervisors (designed for 3.3v and 3v systems) doesn't always connect v battery to v out when v battery is greater than v cc . v battery connects to v out (through a 15 w switch) when v cc is below v sw and v battery is greater than v cc .
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 14 switchover at v sw (2.40v) ensures that battery- backup mode is entered before v out gets too close to the 2.0v minimum required to reliably retain data in cmos ram. switchover at higher v cc voltages would decrease backup-battery life. when v cc recovers, switchover is deferred until v cc rises above the reset threshold, v rst , to ensure a stable supply. v out is connected to v cc through a 1.5 w pmos power switch. using a high capacity capacitor as a backup power source f igure 21 shows two ways to use a high v alue capacitor as a backup power source. the high v alue capacitor may be connected through a diode to the 3v input as in f igure 21a or , if a 5v supply is also available, the high v alue capacitor may be charged up to the 5v supply as in figure 21b allowing a longer backup period. since v ba ttery can exceed v cc while v cc i s a b o v e t h e r e s e t t h r e s h o l d , t h e r e a r e n o s p e c i a l p r e c a u t i o n s w h e n u s i n g t h e s e m p supervisors with a high v alue capacitor . o p e r a t i o n w i t h o u t a b a c k u p p o w e r source t h e s e m p s u p e r v i s o r s w e r e d e s i g n e d f o r battery-backed applications. if a backup power source is not used, connect both vbattery and v out to v cc . since there is no need to switch over to any backup power source, v out does not need to be switched. a direct connec- tion to v cc eliminates any voltage drops across the switch which may push v out below v cc . replacing the backup battery if v battery is decoupled with a 0.1 m f capacitor to ground, the backup battery can be removed while v cc remains valid without danger of triggering reset/reset. as long as v cc stays above v sw , battery-backup mode cannot be entered. adding hysteresis to the power-fail comparator the power-fail comparator has a typical input hysteresis of 10mv. this is sufficient for most applications where a power-supply line is being monitored through an external voltage divider (refer to the monitoring an additional power supply section). if additional noise margin is desired, connect a resistor between pfo and pfi as shown in figure 22a . select the ratio of r1 and r2 such that pfi sees 1.25v when v in falls to its trip point (v trip ). r3 adds the hysteresis and will typically be more than 10 times the value of r1 or r2. the hysteresis window extends both above (v h ) and below (v l ) the original trip point (v trip ). v cc 3.0v or 3.3v gnd v battery v out connect to st a tic ram to m p 0.1f connect pin 7* 1n4148 v cc 3.0v or 3.3v gnd v battery v out reset for the sp690t/s/r and the sp802t/s/r reset for the sp804t/s/r and the sp805t/s/r * connect to st a tic ram to m p 0.1f connect pin 7* 1n4148 +5v figure 21. using a high capacity capacitor as a backup power source a) b)
15 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation connecting an ordinary signal diode in series with r3, as in figure 22b , causes the lower trip point (v l ) to coincide with the trip point without hysteresis (v trip ), so the entire hysteresis window occurs above v trip . this method pro- vides additional noise margin without compro- mising the accuracy of the power-fail threshold when the monitored voltage is falling. it is useful for accurately detecting when a voltage falls past a threshold. figure 22a. adding additional hysteresis to the power-fail comparator. figure 22b. shifting the additional hysteresis above v pft the current through r1 and r2 should be at least 1 m a to ensure that the 25na (max over extended temperature range) pfi input current does not shift the trip point. r3 should be larger than 10k w so it does not load down the pfo pin. capacitor c1 adds additional noise rejection. figure 23. using the power-fail comparator to monitor an additional power supply v in r1 r2 + r3 to m p pfi pfo gnd v cc sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r pfo 0v 0v v l v trip v h v in v in r1 r2 + r3 to m p pfi pfo gnd v cc sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r pfo 0v 0v v trip v h v in *optional v trip = v pft v h = v l = r1 where v pft = 1.25v v pfh = 10mv r1 + r2 r2 ( ) v pft + v pfh ( ) r1 ( ) 1 + 1 + 1 r1 r2 r3 ( ) v pft [ ( 1 + 1 + 1 r1 r2 r3 ) - v cc r3 ] v trip = v pft v l = r1 where v pft = 1.25v v pfh = 10mv v d = diod forward vol t age drop r1 + r2 r2 ( ) v pft + v pfh [ ( 1 + 1 + 1 r1 r2 r3 ) - (v cc - v d ) r3 ] ( ) *c1 *c1 r1 r2 v- pfi pfo gnd v cc sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r pfo v l v trip v- v in r1 r2 pfi pfo gnd v cc sp690t/s/r sp802t/s/r sp804t/s/r sp805t/s/r pfo v trip v h v in v cc 0v 3.0v or 3.3v v cc v trip = r2 v l = r2 where v pft = 1.25v v pfh = 10mv note: v trip is nega tive v pft + v pfh ( ) 1 + 1 r1 r2 ( ) v pft [ ( 1 + 1 r1 r2 ) - v cc r3 ] [ - v cc r1 ] v trip = v pft v h = r1 + r2 r2 ( ) v pft + v pfh ( r1 + r2 r2 ) ( ) a.) b.)
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 16 figure 24. interfacing to microprocessors with bidirectional reset i/o v cc gnd v cc gnd reset reset 4.7k w m p buffered reset connects to system components monitoring an additional power supply these m p supervisors can monitor either positive or negative supplies using a resistor voltage divider to pfi. pfo can be used to generate an interrupt to the m p, as seen in figure 23 . interfacing to m ps with bidirectional reset pins any m ps with bidirectional reset pins, such as the motorola 68hc11 series, can interface with the sp690_ and the sp802_ reset outputs. for example, if the reset output is driven high and the m p wants to pull it low, indeterminate logic levels may result. to correct this, connect a 4.7k w resistor between the reset output and the m p reset i/o, as in figure 24. buffer the reset output to other system components. negative-going v cc transients while issuing resets to the m p during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short- d u r a t i o n n e g a t i v e - g o i n g v c c t r a n s i e n t s (glitches). it is usually undesirable to reset the m p when v cc experiences only small glitches. figure 25 shows maximum transient duration vs. reset-comparator overdrive, for which reset pulses are not generated. the data was generated using negative-going v cc pulses, starting at 3.3v and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). the graph shows the maximum pulse width a negative-going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e. goes farther below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc transient that goes 100mv below the reset threshold and lasts for 40 m s or less will not cause a reset pulse to be issued. a 100nf bypass capacitor mounted close to the v cc pin provides additional transient immunity. figure 25. maximum transient duration without causing a reset pulse vs. reset comparator overdrive 1nf capacitor v out to gnd above line reset generated no reset generated
17 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e package: plastic dual?n?ine (narrow) dimensions (inches) minimum/maximum (mm) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) a2 b b1 c d e e1 l 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.735/0.775 (18.669/19.685) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.355/0.400 (9.017/10.160) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 22?in 8?in 14?in 16?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.145/1.155 (29.083/29.337) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.780/0.800 (19.812/20.320) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 18?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.880/0.920 (22.352/23.368) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15? 20?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.980/1.060 (24.892/26.924) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0? 15 (0?15?
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 18 d e h package: plastic small outline (soic) (narrow) dimensions (inches) minimum/maximum (mm) 8?in a a1 l b e h x 45 a a1 b d e e h h l 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249 0.014/0.019 (0.35/0.49) 0.189/0.197 (4.80/5.00) 0.150/0.157 (3.802/3.988) 0.050 bsc (1.270 bsc) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 14?in 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508) 0.337/0.344 (8.552/8.748) 0.150/0.157 (3.802/3.988) 0.050 bsc (1.270 bsc) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0?8? (0?8? 16?in 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508) 0.386/0.394 (9.802/10.000) 0.150/0.157 (3.802/3.988) 0.050 bsc (1.270 bsc) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0?8? (0?8?
19 sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation ordering information model temperature range package types sp690tcn......................................................0 c to +70 c...................................................... 8-pin nsoic sp690tcp......................................................0 c to +70 c.........................................................8-pin pdip sp690ten.....................................................-40 c to +85 c....................................................8-pin nsoic sp690tep.....................................................-40 c to +85 c....................................................... 8-pin pdip sp690scn......................................................0 c to +70 c......................................................8-pin nsoic sp690scp......................................................0 c to +70 c.........................................................8-pin pdip sp690sen.....................................................-40 c to +85 c....................................................8-pin nsoic sp690sep.....................................................-40 c to +85 c.......................................................8-pin pdip sp690rcn......................................................0 c to +70 c......................................................8-pin nsoic sp690rcp......................................................0 c to +70 c.........................................................8-pin pdip sp690ren.....................................................-40 c to +85 c....................................................8-pin nsoic sp690rep.....................................................-40 c to +85 c.......................................................8-pin pdip sp802tcn........................................................0 c to +70 c.................................................. ..8-pin nsoic sp802tcp........................................................0 c to +70 c....................................................... 8-pin pdip sp802ten.......................................................-40 c to +85 c................................................ ..8-pin nsoic sp802tep.......................................................-40 c to +85 c..................................................... 8-pin pdip sp802scn........................................................0 c to +70 c....................................................8-pin nsoic sp802scp........................................................0 c to +70 c.......................................................8-pin pdip sp802sen.......................................................-40 c to +85......................................................8-pin nsoic sp802sep.......................................................-40 c to +85 c.....................................................8-pin pdip sp802rcn........................................................0 c to 0 c........................................................8-pin nsoic sp802rcp........................................................0 c to+70 c...................................................... 8-pin pdip sp802ren.......................................................-40 c to +85 c..................................................8-pin nsoic sp802rep.......................................................-40 c to +85 c.....................................................8-pin pdip sp804tcn.......................................................0 c to +70 c................................................... ..8-pin nsoic sp804tcp.......................................................0 c to +70 c........................................................ 8-pin pdip sp804ten......................................................-40 c to +85 c................................................. ..8-pin nsoic sp804tep......................................................-40 c to +85 c...................................................... 8-pin pdip sp804scn.......................................................0 c to +70 c.....................................................8-pin nsoic sp804scp.......................................................0 c to +70 c........................................................8-pin pdip sp804sen......................................................-40 c to +85 c...................................................8-pin nsoic sp804sep......................................................-40 c to +85 c......................................................8-pin pdip sp804rcn.......................................................0 c to +70 c.....................................................8-pin nsoic sp804rcp.......................................................0 c to +70 c........................................................8-pin pdip sp804ren......................................................-40 c to +85 c...................................................8-pin nsoic sp804rep......................................................-40 c to +85 c......................................................8-pin pdip sp805tcn........................................................0 c to +70 c.................................................. ..8-pin nsoic sp805tcp........................................................0 c to +70 c....................................................... 8-pin pdip sp805ten.......................................................-40 c to +8c.................................................. ..8-pin nsoic sp805tep.......................................................-40 c to +85 c..................................................... 8-pin pdip sp805scn........................................................0 c to+70 c.....................................................8-pin nsoic sp805scp........................................................0 c to +70 c.......................................................8-pin pdip sp805sen.......................................................-40 c to +85 c..................................................8-pin nsoic sp805sep.......................................................-40 c to +85 c.....................................................8-pin pdip sp805rcn........................................................0 c to +70 c....................................................8-pin nsoic sp805rcp........................................................0 c to +70 c.......................................................8-pin pdip sp805ren.......................................................-40 c to +85 c..................................................8-pin nsoic sp805rep.......................................................-40 c to +85 c.....................................................8-pin pdip please consult the factory for pricing and availability on a tape-on-reel option.
sp690t/s/r jan 30-06 sp690t/s/r, 802/t/s/r, 804t/s/r, 805t/s/r low power microprocessor supervisory ? 2006 sipex corporation 20

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